1. Field of the Invention
The present invention relates to the field of semiconductor processing and more particularly to a method of fabricating a multi-cornered semiconductor film and a multi-cornered tri-gate transistor.
2. Discussion of Related Art
In order to increase the performance of modern integrated circuits, such as microprocessors, silicon on insulator (SOI) transistors have been proposed. Silicon on insulator (SOI) transistors have an advantage in that they can be operated in a fully depleted manner. Fully depleted transistors have an advantage of ideal subthreshold gradients for optimized ON current/OFF current ratios.
An example of a proposed SOI transistor which can be operated in a fully depleted manner is a nonplanar or tri-gate transistor 100, such as illustrated in FIG. 1. Tri-gate transistor 100 includes a silicon body 104 formed on an insulating substrate 102 having a buried oxide layer 103 formed on a monocrystalline silicon substrate 105. A gate dielectric layer 106 is formed on the top and sidewalls of the silicon body 104 as shown in FIG. 1. A gate electrode 108 is formed on the gate dielectric layer and surrounds the body 104 on three sides, essentially providing a transistor 100 having three gate electrodes (G1, G2, G3), one on each of the sidewalls of the body 104 and one on the top surface of the body 104. A source region 110 and a drain region 112 are formed in the body 104 on opposite sides of the gate electrode 108 as shown in FIG. 1. The active channel region is the region of the silicon body beneath gate electrode 108 and between the source 110 and drain 112 regions.
An advantage of the tri-gate transistor 100 is that it exhibits superior short channel effects (SCE). One reason tri-gate transistor 100 exhibits superior short channel effects, is because the gate electrode 108 surrounds the active channel region on three sides. It has been determined that the corners 140 and 142 of the body exhibit near ideal subthreshold characteristics and are superior to those shown by the non-coener (sidewalls 130 and 132) portions of the device. In the subthreshold region and at low gate voltages the corners of the device dominate the full transistor characteristics. Above the threshold voltage, the larger non-corner portions of the channel region dominate transistor characteristics.